1. Field of the Invention
The present invention relates to a digital-to-analog converting circuit (hereinafter referred to also as a digital-analog converting circuit or DA converting circuit), and more particularly to a DA converting circuit having an offset canceling function to correct an offset of analog output voltage due to a bias of the characteristics of the DA converting circuit itself, namely, a self-calibration function.
2. Related Art
As literature concerning the prior art in the above-mentioned field, there is Japanese Patent Application Laid-Open No. 11-234130.
FIG. 2 is a block diagram of a conventional DA converting circuit 100 disclosed in the above-mentioned literature.
A DA converting circuit 100 includes a selector (SEL) 1. The output terminal of the selector 1 is connected to the first input terminal of a digital adder (ADD) 2, which has two input terminals. The selector 1, according to a mode signal (MOD), selects a digital input signal (IN) as a digital signal to be converted into an analog output voltage or a fixed data (FD) as a digital signal having a fixed value, and outputs it to the digital adder 2.
The,output terminal of the digital adder 2 is connected to the input terminal of a digital-to-analog converter 3 (hereafter referred to as xe2x80x9cDACxe2x80x9d) to convert a digital signal to an analog voltage. The output terminal of the DAC 3 is connected to a non-inverting input terminal of an operational amplifier (AMP) 4 as a component part of a buffer circuit. The operational amplifier 4 outputs an analog output signal (OUT) and part of the analog signal is fed back to an inverting input terminal of the operational amplifier 4. The operational amplifier 4 functions as a buffer circuit to prevent effects of noise from the circuit of the output terminal that receives the analog output.
In an operation of the DA converting circuit 100, a digital input signal (IN), while passing through the component parts mentioned above, is converted into an analog voltage, and the analog voltage as an outcome of the conversion is output as an analog output signal (OUT) from the operational amplifier 4.
To calibrate the analog output signal (OUT), the DA converting circuit 100 is configured as follows.
The analog output signal (OUT) from the operational amplifier 4 is applied to the first input terminal of a comparator (COMP) 5. A reference voltage (VC) at an analog voltage value corresponding to the digital value of the fixed data (FD) is applied to the other (second) input terminal of the comparator 5. The comparator 5 compares the analog output voltage (OUT) and the reference voltage (VC) applied to the input terminals thereof and outputs a binary signal, that is, a digital signal representing the result of comparison. The output terminal of the comparator 5 is connected to input terminals of a counter (CNT) 6 and a register latch (REG) 7. The counter 6 counts up an estimated offset value one-by-one at fixed time intervals to obtain offset values of the analog output signal (OUT), and successively outputs the estimated offset values to the register latch 7. The register latch 7 applies the estimated offset value from the counter 6 to the second input terminal of the digital adder 2, and stores as an offset value an estimated offset value when the result of comparison from the comparator 5 is inverted.
In the calibration prior to an ordinary conversion operation in the DA converting circuit 100, the following operation takes place.
When a mode signal (MOD) specifying that an operation be performed in the offset value measuring mode is supplied to the selector 1, a digital value corresponding to the reference voltage (VC) applied to the comparator 5 is input as fixed data (FD) of eight bits, for example, to the first input terminal of the digital adder 2. In this case, for example, xc2xd of the analog power supply voltage (Vcc) is supplied.as the reference voltage (VC), and 7Fh (h indicates hexadecimal notation and 7Fh means an intermediate value) is supplied as a digital value.
At this time, the counter 6 outputs an 8-bit digital signal corresponding to 80h as an initial value of an estimated offset value to the register latch 7. The register latch 7 stores this estimated offset value, and outputs this estimated value to the digital adder 2.
When receiving the estimated offset value from the register latch 7 at its second input terminal, the digital adder 2 adds the estimated value and the value of fixed data supplied from the selector 1. When the result of addition is sent from the digital adder 2 to the DAC 3, a digital signal representing the result of addition is converted by the DAC 3 into an analog voltage, and the operational amplifier 4 outputs it as an analog signal OUT. The analog signal OUT, as mentioned above, is input to the comparator 5 and is compared with the reference voltage (VC), and a binary signal representing the result of comparison is output to the counter 6 and the register latch 7.
After this, an estimated offset value that is output from the counter 6 is counted up by addition of ones and zeros from 80h to a maximum of 7Fh at fixed time intervals. Consequently, as the result of addition at the digital adder 2, by which the digital input to the DAC 3 increases gradually, the analog output signal (OUT) increases. When the analog output signal (OUT) exceeds the reference voltage (VC), a binary signal, representing the result of comparison output from the comparator 5, is inverted. The register latch 7 stores as an offset value an estimated offset value when the binary signal is inverted.
When the offset value has been set, to proceed from the calibration to an ordinary conversion operation, a mode signal (MOD), which specifies the DA conversion mode for a conversion operation, is supplied to the selector 1. In response to what is specified by the mode signal (MOD), the digital input signal (IN) is applied to the first input terminal of the digital adder 2. At this time, the register latch 7 outputs to the digital adder 2 as a correction value the offset value measured in the offset measuring mode. The digital input signal (IN) is added with the correction value, and converted by the DAC 3 into an analog voltage, which is output by the operational amplifier 4 as an analog output signal (OUT).
As has been described, in the conventional DA converting circuit 100, before performing an ordinary DA conversion operation, an offset value is measured, in other words, a calibration is carried out. By this calibration, an offset value is measured, which makes it possible to appropriately output an analog voltage that has a similar value to the reference voltage (VC) corresponding to a digital signal IN. This offset value is stored in the register latch 7. In an ordinary DA conversion, the stored offset value is added as a correction value to a digital input signal IN. Therefore, according to a conventional DA converting circuit 100, offsets that are liable to occur in the DAC 3 and the operational amplifier 4 can be cancelled in an ordinary DA conversion.
A conventional DA circuit, however, has a problem as follows.
As described above, a conventional DA circuit 100 includes a digital adder 2 to add an 8-bit digital signal IN and an 8-bit offset value, and a DAC 3 to convert a result of addition by the digital adder into an analog voltage. In such a circuit configuration, if for example a permissible number of digits in conversion at the DAC 3 is eight bits, the same as the number of digits of a digital signal IN, then if the DAC 3 receives a digital signal of nine bits produced by a carry from a result of addition in the digital adder 2, an overflow occurs, with the result that precision decreases in conversion to an analog output voltage.
Therefore, an object of the present invention is to provide a DA converting circuit capable of avoiding a drop in conversion precision ascribable to an overflow in the DA converter.
According to an aspect of the present invention, a digital-to-analog converting circuit comprises a first digital-to-analog converter for outputting an analog voltage corresponding to a value of a digital input signal (IN), and a calibration mechanism for generating a correction signal to eliminate an offset related to a conversion operation of the converter, the calibration mechanism comprises a correction value setting section for generating a digital correction signal (CAL) to eliminate the offset, a second digital analog converter for converting the digital correction signal generated by the correction value setting section into an analog voltage, and an analog adder for adding the analog voltage output from the second converter and the analog voltage output from the first converter, and outputting a digital-to-analog-converted value representing a result of addition.
According to another aspect of the present invention, the calibration mechanism may further comprise a first selector for selectively inputting the digital input signal or a data signal (FD) for performing a calibration to generate the digital correction signal to the first digital-to-analog converter, the correction value setting section may comprise a comparator for, when the data signal is selected by the first selector, comparing output values from the analog adder with a reference value, and outputting comparison results sequentially, a register for storing the plurality of comparison results from the comparator, and a controller (16) for sequentially transferring a plurality count signals, instead of the correction signal, having progressively increasing or decreasing value to the second digital analog converter.
According to a further aspect of the present invention, in performing the calibration, the register may sequentially store comparison results according to the count signals, and the controller may obtain a correction value to eliminate the offset based on the count values when the comparison results stored in the register change, and in the conversion operation such that the digital input signal is selected by the first selector, may output a digital signal having the correction value as the correction signal to the second digital-to-analog converter.
According to yet another aspect of the present invention, the calibration mechanism may further comprise a second selector, located between the controller and the second digital-to-analog converter, selectively outputting the digital correction signal from the controller or an external digital correction signal input from outside as the correction value to the second digital-to-analog converter, and in the conversion operation, the second selector selects either the correction signal or the external correction signal.
According to a still further aspect of the present invention, the calibration mechanism may further comprise a second selector for selectively outputting a first digital supplementary signal input from outside to modify the digital correction signal or a second digital supplementary signal having a value different from the first supplementary signal, and may comprise a digital adder, located between the controller, the second selector and the second digital-to-analog converter, for adding a digital output value from the second selector and a digital output value from the controller, and for outputting a result of the addition to the second digital-to-analog converter.
According to a still other aspect of the present invention, the digital adder, during the calibration, may sequentially output a result of addition of each value of the plurality of count signals and the value of the first supplementary signal to the second converter, and when correcting the value of the digital correction signal, may output a result of addition of the value of the correction signal and the value of the second supplementary signal to the second converter.
According to an additional aspect of the present invention, the first digital supplementary signal (FX) may have a value of level xe2x80x9c0xe2x80x9d to substantially invalidate the addition function of the digital adder, and the second digital supplementary signal (DTO) may have a value to finely adjust the value of the digital correction signal.
According to another aspect of the present invention, the analog adder may output an analog reciprocal or differential value, reciprocal to the result of addition at the analog adder, as the reference value to the comparator with outputting the result of addition, the reciprocal value of the analog adder in the calibration changes reciprocally to change the analog calculation result, and the comparator may output comparison results between a plurality of the addition results having progressively decreasing or increasing value and a plurality of reciprocals of the addition results that change reciprocally to the addition results.